1. Field of the Invention
The present invention relates to a microprocessor, more particularly, it relates to a microprocessor which executes instructions at a high speed in normal mode by applying pipeline processing, and at a testing, the microprocessor diagnoses all the internal function blocks by executing test instruction based on the dedicated mode exclusively available for executing test, so that a test of the microprocessor is done with ease.
2. Description of Related Art
Generally, any conventional microprocessor incorporates an instruction set of a single system. In order to execute the instruction set at an extremely fast speed, the interior of such a conventional processor is divided into a plurality of function blocks, in which respective function blocks are operated in parallel with each other based on the principle of pipeline processing.
FIG. 1 illustrates an example of the simplified block diagram of the whole structure of a conventional microprocessor.
The reference numeral 101 shown in FIG. 1 designates an instruction fetch unit which delivers an address to a memory external to the microprocessor via an address output circuit 108, and then fetches an instruction via a data input/output circuit 109.
The reference numeral 102 designates an instruction decoding unit which decodes the instruction received from the instruction fetch unit 101, and then outputs information needed to executing the received instruction.
The reference numeral 103 designates an instruction execution control unit. The instruction execution control unit 103 outputs a microprogram entry address, which is outputted from the instruction decoding unit 102, to a microprogram counter 106, and controls an instruction execution unit 105 according to a microinstruction read out from a micro ROM 107 based on an address outputted from the microprogram counter 106, and information such as a general purpose register number, a literal operand and a data size outputted from the instruction decoding unit 102 in order to execute the instruction decoded in the instruction decoding unit 102. Using the microinstruction outputted from the micro ROM 107 by addresses sequentially indicated by the microprogram counter 106 and other information outputted from the instruction decoding unit 102, the instruction execution control unit 103 controls an instruction execution unit 105 to execute instructions.
The reference numeral 104 designates an operand access unit. In the case where an operand needed for executing instructions is stored in memory, the operand access unit 104 fetches the needed operand through the data input/output circuit 104 by outputting an address of the needed operand to the memory external to the microprocessor via address output circuit 108.
In the case where an operand should be stored in the memory, the operand access unit 104 outputs the operand address to the memory external to the microprocessor via the address output circuit 108 and delivers the operand to the memory via the data input/output circuit 109 in order to store the operand in the memory.
Those function blocks including the instruction fetch unit 101, instruction decoding unit 102, and the instruction execution unit 105 operate themselves in parallel and in association with each other, and based on the principle of pipeline processing, these function units simultaneously execute a plurality of instructions.
U.S. Pat. No. 4,402,042 entitled "MICROPROCESSOR SYSTEM WITH INSTRUCTION PRE-FETCH" discloses such a microprocessor featuring enhanced performance capable of simultaneously executing a plurality of instructions by applying pipeline processing.
Independent of the instruction system for pipeline processing for achieving higher performance mentioned above, such a conventional microprocessor capable of executing such an instruction system for utilizing existing software is also well known. As example of such microprocessor was introduced in the "NIKKEI ELECTRONICS, on pages 199 through 204, in Vol. No. 391, issued on Mar. 24, 1986, by Sato et al, entitled "32-bit microprocessor V60 incorporating virtual memory control system and floating point operation function".
When testing respective function blocks, any conventional microprocessor self-diagnoses the operation of the microprocessor by applying either an instruction system for achieving higher performance of pipeline processing like the one cited above or by applying such an instruction system utilizing the existing software. Either of these instruction systems allows a plurality of function blocks inside of the microprocessor to operate themselves in parallel with each other by applying pipeline processing. When executing instructions, since respective function blocks operate themselves in association and in parallel with each other, the size of the operational pattern significantly increases. And yet, since the microprocessor is composed on a single LSI chip, it is extremely difficult to measure the voltage or current of nodes other than those connected to external pins of the chip. From the standpoint of saving testing costs, it is desired that the microprocessor be testable by the application of Test data to the external pins only.
In order to diagnose each function block of a microprocessor, it is necessary for the test system to preliminarily execute an instruction which initializes the content of various latches inside the microprocessor or the test system must operate by combining these instructions so that those function blocks other than those which are subject to diagnosis cannot adversely affect the diagnosing operation. Actually, the design of a test program is extremely difficult, and a number of man-hours are needed for designing the test program. In particular, it is extremely difficult for testers to precisely detect the cause of an incorrect operation of an experimentally assembled microprocessor when it does not function as designed.
As a means for solving the above problem and easily executing the diagnostic test of an LSI like a microprocessor, a test method has been proposed, which connects the latches inside of the LSI by means of shift path and uses a scan path for causing the latch content to be input and output serially. This proposal was introduced in the "NIKKEI ELECTRONICS", issued on Apr. 18, 1979, on pages 57 through 68, by Tanaka, entitled A Method of Significantly Improving the Detect Rate of Failure of LSI by Applying a Circuit Structure Capable of Easily Executing Test, for example.
There is much significance in the execution of a test of an LSI using the scan path because the values of latches in the LSI can be read and written. Nevertheless, this test method still accompanies these problems to be solved including the need for combining those latches requiring read and write in the course of designing LSI and the problem of much hardware volume needed for changing-over scan path operation and operation of using set value by the scan path operation.
Another test method is also proposed to avoid increasing volume of the hardware by adopting a scan path. After turning the microprocessor into the test mode, this method executes a test of a programmable logic array (PLA), or a ROM, or a cache as an internal memory effectively using internal construction of the microprocessor, or using diagnosing microprogram routine. Such a test method is disclosed in J. R. Kurban and J. E. Salick, "Testing Approaches in the MC68020", VLSI DESIGN, Vol. V, No.11, on pages 22 through 30, November, 1984, for example.
In the above proposed test method, only the diagnosing microprogram routine which is previously stored in the micro ROM can be used because the method which starts the diagnosing microprogram routine by a specified instruction is adopted. Accordingly, when investigating microprocessor faults, it is desirable to execute test instructions corresponding to the cause of the fault, but there is no flexibility in the above test method. Also, in the above test method, microinstructions which are not stored in the micro ROM can not be executed at all, so that more precise diagnostics are not possible.
As cited above, various prior art has been proposed for easily executing a test for microprocessors. Nevertheless, the prior art merely presents methods of partly solving the pending issue. Actually, no art has ever been proposed to thoroughly overcome the difficulty in the detection of the cause of a partial failure occurring in a microprocessor.
It is essential for a manufacturer to repeatedly execute trial production of microprocessors before completing the design of a final product allowing the manufacturer to enter into mass production after overcoming design bugs caused by erroneous microprograms and logical design errors and the lowered yield rate caused by short-circuits between distributed wires as a result of small margins of error in the designed mask pattern. It is extremely important for the manufacturer to detect the cause of failure of a microprocessor as early as possible.
In order to specify a point having too small a margin on the LSI, it is essential for the manufacturers to test by various test programs as many trial products as possible before specifying the point having high potential of causing fault to occur. For this purpose, manufacturers should also quickly design various test programs according to the kinds of failure. In consequence, if the test program could not easily be designed, manufacturers will be obliged to sustain a large number of man-hours before finalizing the design of test programs.